1. Field of the Invention
The invention relates to a discharge circuit, and more particularly to a discharge circuit of a flash memory.
2. Description of the Related Art
Recently, flash memory has been commonly used in ultra large scale integration (ULSI) circuits. Flash memory is a sort of nonvolatile memory, which is characterized by permanently keeping stored data even when power is not supplied. The characteristic is similar to a hard disc. Among the nonvolatile memories, since the flash memory has high speed, high density, in-system reprogramming ability and so on, it is the basic storage media in portable digital electronic devices. The general high speed six-transistor static random access memory (6T SRAM) requires six transistors to form one memory cell, and the high speed dynamic random access memory (DRAM) also requires the area of about four transistor elements for one memory cell. On the contrary, flash memory requires only one element to represent a single memory cell, thus having extremely high density. In addition, since the flash memory adopts a stacked-gate MOSFET structure, the process can also be greatly simplified. Therefore, flash memory is the preferred choice for storage media in portable digital electronic devices or large data storage media. The flash memory is especially commonly used for voice signal processing in mobile phones and video data processing in personal digital assistants.
Flash memory can be grouped into NAND flash and NOR flash. The memory cell of a NAND flash is structured in serial and the writing and reading of the memory cell is processed by pages and blocks, where one page contains several bits, and one block contains several pages. Typical block sizes are 8˜32 KB. The advantage of the serial structure is that the memory size may be made large, thus, the memory size of a NAND flash generally exceeds 512 MB. Also, NAND flash is now being commonly used because of its low cost. The memory cell of a NOR flash is structured in parallel and thus, the transmission of the input/output port of the NOR flash is faster than the NAND flash. Due to the parallel transmission mode, reading in the NOR flash is faster than in the NAND flash. NAND flash is greatly used in portable storage devices, digital cameras, MP3 players, personal digital assistants, and so on.
FIG. 1 shows the cross-sectional view of a flash memory 10. As shown in FIG. 1, the label P_sub stands for the substrate, the labels P_well and LV_P well stand for the P well, and the label N_well stands for the N well. The flash memory 10 includes a memory cell, a selection transistor, and multiple voltage lines providing voltage to operate the flash memory. The label WL stands for the word line, and the label BL stands for the bit line connected between the memory cell and selection transistor. The selection voltage line SL is connected to the memory cell, and the P well voltage line VPW is connected to the P well of the memory cell. The voltage line YBL is connected to the gage of the selection transistor, and the voltage line Virpwr is also connected to the selection transistor.
FIG. 2 shows the conventional voltage on each voltage line when erasing of the flash memory. As shown in FIG. 2, during the time interval A, an external voltage source (not shown) supplies an erasion voltage Verase to the voltage line VPW to provide a logic high voltage to the P well. Thus, the electrons in the written floating gate (FG as shown in FIG. 1) can be sucked back to the P_well along the direction as shown in the arrows of FIG. 1, so as to erase the written data in the flash memory 10. The described operation is called the F-N tunneling to erase the stored data in the flash memory. During the time interval A, the selection voltage line SL, bit line BL, and voltage lines YBL and Virpwr are all floating, and thus, will be coupled to a voltage smaller than that of the voltage line VPW. For example, as shown in the figure, when the 20V erasion voltage Verase is supplied to the voltage line VPW, the voltages on SL, BL, YBL and Virpwr are coupled to the voltages smaller than 20V to sustain appropriate operations of the flash memory. When the data is completely erased, the voltage lines begin to discharge during time interval B. However, since the discharge speed of each element in the flash memory is different, the remaining voltage on each element may be different and therefore conducting the PN junction and causing a large current which may damage the flash memory.
Therefore, an improved discharge circuit to adequately control the discharge procedure of each voltage line for discharging at the same time and achieving stable voltages is highly desired.